The present invention relates generally to semiconductor integrated circuits, and more particularly to register and latch circuits.
The operating speeds of semiconductor devices continue to rise. Many integrated circuits include input circuits for latching input data. For example, many semiconductor devices are xe2x80x9csynchronousxe2x80x9d devices that latch input data in synchronism with a system clock. In addition, many integrated circuits can include output circuits that latch output data in response to a system clock. Still further, some integrated circuits have intermediate pipelined sections that may latch and/or shift data in response to a system clock. As device speeds increase, it can be important to reduce the time required for all aspects of device operation, including the time required to latch an input signal, and/or an output value and/or latch values in intermediate pipelined stages.
The operation of the disclosed embodiments may best be understood by first referring to a conventional register circuit.
FIG. 7 shows a conventional register circuit. The conventional register circuit is designated by the general reference character 700 and may include a master latch 702 and a slave latch 704. A master latch circuit 702 can have an input (IN) that receives an input value, and can latch data in response to a clock signal CLK. A slave latch 704 can have an output (OUT) that provides a latched value, and can also latch data in response to the clock signal CLK.
A master latch circuit 702 can store data when the CLK signal has a low level. In addition, with the CLK signal level low, the output of the master latch circuit 702 is prevented from being input into the slave latch circuit 704.
In the above-described arrangement, when the CLK signal transitions high, the input IN is disconnected from the internal circuits of the master latch circuit 702. At the same time, the output of master latch circuit 702 is input to the slave latch circuit 704, and provided as an output from the slave latch (OUT).
In synchronous devices, the clock signal CLK transitions between levels in a periodic fashion. Thus, in the example described above, each low-to-high transition can result in an output value at the output (OUT).
Next, the particular composition of a latch circuit will be described in more detail. FIG. 7 shows the details of slave latch circuit 704. A slave latch circuit 704 may include an input connected to the output of master latch circuit 702. The input of the slave latch circuit 704 can be further connected to the source-drain paths of a p-channel metal-oxide-semiconductor (PMOS) transistor M71 arranged in parallel with an n-channel MOS (NMOS) transistor M72. The gate of NMOS transistor M72 receives the clock signal CLK, while the gate of PMOS transistor M71 receives an inverted clock signal /CLK by way of an inverter INV71.
The slave latch circuit 704 further includes an inverter INV72 for driving the output of the slave latch 704 (and hence the register 700) in this case. The inverter INV72 can have an input connected to the source-drain paths of transistors M71/M72, and an output connected to output OUT. An inverter INV73 has an input connected to the output OUT, and an output connected to the source-drain paths of a PMOS transistor M73 arranged in parallel with an NMOS transistor M74. The gate of NMOS transistor M74 receives the inverted clock signal /CLK by way of inverter INV71, while the gate of PMOS transistor M73 can receive the clock signal CLK directly.
In the slave latch circuit 704 illustrated, when the clock signal CLK is high, transistors M71 and M72 are turned on while transistors M73 and M74 are turned off. Thus, the output from master latch 702 can be driven on output OUT by inverter INV72. In contrast, when the clock signal CLK is low, transistors M71 and M72 are turned off while transistors M73 and M74 are turned on. The data at the output OUT can be fed back through inverter INV73 to the input of inverter INV72, thus forming a flip-flop. In this way, the data value can continue to be held (latched) in the slave latch circuit 704.
In a conventional integrated circuit, a register circuit may have adjacent circuits that can present large loads. More particularly, an input register circuit may have an output connected to an internal driver circuit that drives various internal lines of the integrated circuit. An output register circuit may have an output connected to an output driver circuit that outputs data from the integrated circuit. Such large loads can add to signal propagation times.
Further, the load that must be driven by the clock signal can also be high. More particularly, while the clock signal CLK of FIG. 7 is shown driving two latch circuits (702 and 704), such a clock signal CLK may have to drive many such circuits.
One way to improve the speed in a conventional register circuit has been to attempt to reduce the input capacitance for the clock signal CLK. Gate capacitance can be reduced by decreasing the gate size of transistors M72 and M73 and the gates of transistors within inverter INV71. Such an approach can have limits, however. Reducing the size of transistors M72 and M73 can increase the xe2x80x9conxe2x80x9d impedance of their respective transfer gates, increasing signal propagation time. Further, decreasing the size of transistors within inverter INV71 can reduce the driving strength of the inverter, which can further reduce the speed at which the transfer gates can turn on and off.
In addition to operating speed, another feature of an integrated circuit that may be considered valuable is that of current consumption. Lower current consumption can be desirable as power supplies may have limited current supply capabilities. Further, lower current consumption can translate directly into lower power consumption. Reductions in power consumption are particularly desirable in portable electronic devices that operate on batteries.
Yet another important feature of an integrated circuit is the amount of area that is required for such a circuit. The more area that an integrated circuit requires, the more expensive the device may be to manufacture.
It would be desirable to arrive at some way of improving the speed of a latching and/or register circuit. Such a faster circuit could contribute to a faster overall integrated circuit.
It would also be desirable if such a circuit did not significantly increase power and/or current consumption over conventional approaches.
It would be further desirable if such a circuit did not require a considerable amount of area over conventional approaches.
A register circuit according to the present invention may include a master latch circuit and a slave latch circuit arranged in series with one another. A slave latch circuit may include a first driver transistor that can drive an output node to a first potential and a second driver transistor that can drive the output node to a second potential. A first controllable impedance path can connect the control terminal of the first driver transistor to the output of the master latch circuit. A second controllable impedance path can connect the control terminal of the second driver to the output of the master latch circuit. The first and second controllable impedance paths can be enabled according to a clock signal.
The above arrangement, the controllable impedance paths can transfer an input signal to the respective driver transistor control terminals, and not a flip-flop type circuit, and thus may allow for faster operating speeds.
According to one aspect of the embodiments, the controllable impedance paths may include transistors, more particularly, insulated gate field effect transistors. Further, the transistor of the first controllable impedance path can have a conductivity that is different from the first driver transistor. Similarly, the transistor of the second controllable impedance path can have a conductivity that is different from the second driver transistor. In one arrangement, the first driver transistor can be a p-type transistor and the first controllable impedance path can include an n-type transistor that receives a clock signal at its control terminal. The second driver transistor can be an n-type transistor and the second controllable impedance path can include a p-type transistor that receives an inverted clock signal at its control terminal.
According to another aspect of the embodiments, the slave latch circuit may include a latched state where the data from the master latch circuit is latched within the slave latch circuit. The slave latch circuit may further include a first disable device connected to the control terminal of the first driver transistor and a second disable device connected to the control terminal of the second driver transistor. The first and second disable devices can turn the first and second driver transistors off in the latched state.
According to another aspect of the embodiments, the slave latch circuit may include a flip-flop circuit that can store data. The flip-flop circuit can include transistors having a smaller size than the first and/or second driver transistor. The transistors of the flip-flop circuit may also be smaller than transistors of the first and second controllable impedance paths.
According to another aspect of the embodiments, the slave latch circuit may include a flip-flop circuit that having a passgate between the output of the flip-flop circuit and the output of the slave latch circuit. The passgate circuit may include p-type and n-type transistors having source-drain paths arranged in parallel. The gate of the p-type passgate transistor can receive a clock signal while the gate of the n-type passgate transistor can receive an inverted clock signal.
According to another aspect of the embodiments, the slave latch circuit may include a disable path connected to the control terminal of the first driver transistor. When the second driver transistor is turned on, the disable path can provide a disable voltage to the second driver transistor. The disable path may be parallel to the first controllable impedance path.
According to another aspect of the embodiments, a disable path may include a transistor of a first conductivity type. In one arrangement, the control gate of the disable path transistor can receive an inverted clock signal. In another arrangement, the control gate of the disable path transistor can receive an inverted master latch circuit output signal. Such an arrangement can result in a reduced load for a clock signal.
According to another aspect of the embodiments, the slave latch circuit may include a disable path connected to the control terminal of the second driver transistor. When the second driver transistor is turned on, the disable path can provide a disable voltage to the first driver transistor. The disable path may be parallel to the second controllable impedance path.
According to one aspect of the above latch embodiments, a latch circuit may further include a first disable device connected to the control terminal of the first driver transistor, and a second disable device connected to the control terminal of the second driver transistor. When activated, the first disable device can disable the first driver transistor. Similarly, when enabled, the second disable device can disable the second driver transistor. An input value of one type can activate the first disable device and deactivate the second disable device. An input value of a second type can activate the second disable device and deactivate the first disable device.
According to another aspect of the embodiments, a capacitor can be provided at the input of the slave latch circuit. Such an arrangement can suppress transient rises in potential in the first and second controllable impedance paths when current flows through such paths.
A latch circuit according to the present invention may include a first driver transistor that can drive an output node to a first potential and a second driver transistor that can drive the output node to a second potential. A first controllable impedance path can connect the control terminal of the first driver to an inverted clock signal. A second controllable impedance path can connect the control terminal of the second driver to a clock signal.
The first controllable impedance path can include a first transfer gate that includes a first gate n-type transistor arranged in parallel with a first gate p-type transistor. The control terminal of the first gate n-type transistor can receive an input signal. The control terminal of the first gate p-type transistor can receive an inverted input signal. The second controllable impedance path can include a second transfer gate that includes a second gate n-type transistor arranged in parallel with a second gate p-type transistor. The control terminal of the second gate n-type transistor can receive an inverted input signal. The control terminal of the second gate p-type transistor can receive an input signal.
According to one aspect of the above latch embodiment, a latch circuit may further include a first disable device connected to the control terminal of the first driver transistor, and a second disable device connected to the control terminal of the second driver transistor. When activated, the first disable device can disable the first driver transistor. Similarly, when enabled, the second disable device can disable the second driver transistor. An input value of one type can activate the first disable device and deactivate the second disable device. An input value of a second type can activate the second disable device and deactivate the first disable device.
According to another aspect of the latch embodiments, the first driver transistor and first disable device can include p-type transistors that receive an input signal at their control terminals. The second driver transistor and second disable device can include n-type transistors that receive an inverted input signal at their gates.
According to another aspect of the latch embodiments, the latch circuit may include a flip-flop circuit that can store data. The flip-flop can include transistors having a smaller size than the first and/or second driver transistor. Further, the flip-flop can include transistors having a smaller size than the first and/or second disable device.